fsl_esdhc: Deal with watermark level register related changes
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark
level register description has been changed:
9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00
25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00
Signed-off-by: Priyanka Jain <[email protected]>
Signed-off-by: Poonam Aggrwal <[email protected]>
Tested-by: Stefano Babic <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
projects / project / bcm63xx / u-boot.git / commit